LostCircuits posted a guide on Athlon 64 BIOS Settings
The Command Per Clock sets the Command Rate for the memory controller. At 1T, the controller can issue commands on every clock cycle, if set to 2T, the controller can issue commands only on every other bus cycle. A 2T command rate can be somewhat problematic for a number of reasons. In a first generation DDR architecture, the 2 T command rate can cause bus contention because it can mitigate the advantages of bank interleaving. For example, when using 2:2:2 latency settings, the read command would be issued 2 cycles after a bank activate command. So far so good, according to this there is apparently no need for a 1T CMD rate....Athlon 64 BIOS Settings
