If you were wondering why SSD prices have come down so much over the last few years, a lot of credit has to be given to price wars between various manufacturers. More important than that though, is the ability to shrink flash fabrication process regularly (so far). Only taking cost into consideration, it all comes down to the ability to squeeze as many dies onto a wafer as possible.

As you can see, the move to 20nm has allowed IMFT (the joint foundation of Intel and Micron) to cram 8GB of storage onto a die that is much smaller than the previous fabrication process used in products like the Intel 520 Series and most other MLC flash based SSDs in the current generation: OCZ Vertex 4, Crucial m4, etc. Before that, two dies were used, since a single 8GB 34nm die would be enormous.

Shrinking flash storage comes with its drawbacks though. As dies are shrunk, interference is increased, and write/erase cycle endurance is lowered. For instance, the move from 50nm to 34nm brought the write/erase rate from 10,000 cycles to 3000 (then eventually up to 5000). IMFT were able to maintain that with the move to 25 nm, and they say that 20nm should actually be similar to what that was at the beginning (it’s at 3000 right now). They were able to maintain this endurance in part by improving the fabrication process. For instance, they are using a similar Hi-K dialectric/metal gate technology that allowed them to move to 45nm and beyond on the CPU side in 2008.