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PCStats has posted a new article: Memory Bandwidth vs. Latency Timings



When Intel released the i865PE/i875P dual channel core logic alongside the Intel Pentium 4C processors, the memory game changed forever. With a DDR memory controller now capable of running dual channel, the Pentium 4 was no longer to be bandwidth limited as it had been with the i845 series. Those single channel DDR chipsets, like the i845PE for instance, could only provide half the bandwidth required by the Pentium 4 processor due to its single channel memory controller. As the new 800 MHz FSB Pentium 4 processors allowed users to hit never before seen highs in terms of bus speed, many memory manufacturers were trying to capitalize on the situation by releasing every increasing degrees of "high speed" memory. Unfortunately, to run the memory frequency at the same speed as the FSB (or a 1:1 ratio) almost all the high speed DIMM's (Dual Inline Memory Module) have to have very lax timings. Often, these times are as low as 3-4-4-8!
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