ATI are finally launching their long belated R520 architecture and the
X1800, X1600 and X1300 products based on it. Beyond3D is looking at the architecture and the products based on it.

The memory controller consists of the central controller, or arbiter, with the memory clients surrounding it that can make their data requests to the arbiter. All around the edges of the chip are two 256-bit ring busses, running at same speeds as the DRAM's, which run in opposite directions to reduce latency (dependant on where the data is going to or from it should only have to traverse a maximum of half the ring); by placing the memory bus around the edges of the chip wire density around the controller is decreased, which can result in higher clock speeds.

R520: Radeon X1800 Architecture Preview